As semiconductor devices have become more highly integrated, the design rules for semiconductor devices have been gradually reduced. Accordingly, the areas associated with a contact, which connects individual devices to circuit interconnect wiring in the semiconductor device, and a via contact, which connects an upper interconnect wiring to a lower interconnect wiring, have generally been reduced. In addition, contact depth is generally increasing due to a multi-layered semiconductor device structure.
Consequently, because the resistance of contacts is generally increasing, which may degrade semiconductor device characteristics, technology for reducing contact resistance may be desirable. With contact surface area decreasing and depth increasing, achieving adequate step coverage may be difficult. In other words, the depth of the contact is increased while reducing the area of the contact to increase an aspect ratio so that a process of filling metal in a contact hole without a void or disconnection may be difficult.
FIGS. 1A and 1B are sectional views illustrating a conventional method for forming a metal contact in a semiconductor device. Referring to FIG. 1A, an insulating layer 15 having a contact hole 13 is formed on a silicon substrate 11. A titanium layer 17 and a titanium nitride layer 19 are sequentially formed in the contact hole 13 and on the insulating layer 15 to form a barrier metal layer 21. The titanium layer 17 operates as an ohmic layer and the titanium nitride layer 19 operates as a diffusion barrier layer for preventing the diffusion of a tungsten layer 25 (refer to FIG. 1B), which will be formed in a subsequent process, into the silicon substrate 11. The titanium nitride layer 19 may also improve the surface adhesion of the tungsten, which will be formed in a subsequent process. A thermal process, such as a rapid thermal processing (RTP) or a rapid thermal annealing (RTA), is performed on the silicon substrate 11 having the barrier metal layer 21 so that a titanium silicate 23 layer is formed.
Referring to FIG. 1B, a tungsten layer 25 is formed on the barrier metal layer 21 in order to fill the contact hole 13. The tungsten layer 25 may be formed by chemical vapor deposition (CVD), which has generally effective gap filling characteristics. Because the tungsten layer 25 is formed using CVD, the contact hole 13 is generally efficiently filled with the tungsten layer 25.
Because the titanium silicate 23 layer of FIGS. 1A and 1B has a relatively high level of contact resistance in a highly integrated semiconductor device, however, another material may be substituted for the titanium silicate layer 23. Accordingly, a method for forming a metal contact in a semiconductor device using cobalt silicate will now be discussed.
FIGS. 2A through 2F are sectional views illustrating a conventional method for forming a metal contact in a semiconductor device using cobalt silicide. Referring to FIG. 2A, an insulating layer 33 having a contact hole 32 is formed on a silicon substrate 31. A cobalt layer 35 is formed in the contact hole 32 and on the insulating layer 33 by physical vapor deposition (PVD). In addition, a titanium nitride layer 37 is formed on the cobalt layer 35.
Referring now to FIG. 2B, a first thermal process, such as RTP or RTA, is performed on the silicon substrate 31 on which the cobalt layer 35 and the titanium nitride layer 37 are formed to silicidate the silicon substrate 31 and to form a CoSix layer 39 on the bottom of the contact hole 32.
Referring now to FIG. 2C, the silicon substrate 31, on which the CoSix layer 39 is formed, is dipped in a sulfuric acid solution to strip the cobalt layer 35 and the titanium nitride layer 37 from the contact hole 32 and the insulating layer 33. As a result, the CoSix layer 39 remains on the bottom of the contact hole 32. Because the CoSix layer 39 has a relatively high resistance, the CoSix layer 39 may be transformed into a CoSi2 type cobalt silicide layer by performing a subsequent thermal process.
Referring now to FIG. 2D, a second thermal process, such as RTP or RTA, is performed on the silicon substrate 31 on which the CoSix layer 39 is formed to silicidate the silicon substrate 31 and to form a cobalt silicide 41 layer on the bottom of the contact hole 32. Thereafter, the silicon substrate 31 having the cobalt silicide 41 layer formed thereon is cleaned. Referring now to FIG. 2E, a titanium layer 43 and a titanium nitride layer 45 are sequentially formed on the top surface of the silicon substrate 31 having the cobalt silicide 41 layer to form a barrier metal layer 47.
Referring now to FIG. 2F, a tungsten layer 49 for filling the contact hole 32 is formed on the barrier metal layer 47. The tungsten layer 49 is formed using CVD, which has generally effective gap filling characteristics. Because the tungsten layer 49 is formed using CVD, the contact hole 32 is generally efficiently filled with the tungsten layer 49.
According to the method described with respect to FIGS. 2A through 2F, because the cobalt silicide layer 41 has a generally lower reactivity to dopant than titanium silicide, the cobalt silicide layer 41 can attain a lower contact resistance. Unfortunately, forming a metal contact in accordance with the method of FIGS. 2A through 2F involves performing thermal processes twice and a strip process. In addition, the cobalt layer 35 is formed using PVD according to the method described with respect to FIGS. 2A through 2F, which generally provides poorer step coverage. Accordingly, the thickness of the cobalt layer 35 is typically increased to obtain a cobalt silicide layer 41 having a proper thickness on the contact bottom. When such a thick cobalt layer 35 is deposited, a strip process for removing the cobalt layer 35, which remains after a silicidation process, may be necessary. Furthermore, a reinforced cleaning process is typically performed after the strip processes.